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| a FEATURES Fast (2.2 s) 14-Bit ADC 400 kSPS Throughput Rate 0.3 s Track/Hold Acquisition Time Single Supply Operation Selection of Input Ranges: 10 V, 5 V and 2.5 V 0 V to 2.5 V and 0 V to 5 V High-Speed Parallel Interface which Also Allows Interfacing to 3 V Processors Low Power, 80 mW Typ Power-Saving Mode, 20 W Typ Overvoltage Protection on Analog Inputs Power-Down Mode via STBY Pin AVDD STBY 5 V Single Supply 14-Bit 400 kSPS ADC AD7899 FUNCTIONAL BLOCK DIAGRAM VREF VDRIVE 6k 2.5V REFERENCE AD7899 + - RD TRACK/HOLD VINA VINB DB13 SIGNAL SCALING 14-BIT ADC OUTPUT LATCH DB0 CS BUSY/EOC CONVERSION CONTROL LOGIC INT/EXT CLOCK SELECT INT CLOCK CONVST CLKIN GND OPGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7899 is a fast, low-power, 14-bit A/D converter that operates from a single 5 V supply. The part contains a 2.2 s successive-approximation ADC, a track/hold amplifier, 2.5 V reference, on-chip clock oscillator, signal conditioning circuitry, and a high-speed parallel interface. The part accepts analog input ranges of 10 V, 5 V, 2.5 V, 0 V to 2.5 V, and 0 V to 5 V. Overvoltage protection on the analog input for the part allows the input voltage to be exceeded without damaging the parts. Speed of conversion can be controlled either by an internally trimmed clock oscillator or by an external clock. A conversion start signal (CONVST) places the track/hold into hold mode and initiates conversion. The BUSY/EOC signal indicates the end of the conversion. Data is read from the part via a 14-bit parallel data bus using the standard CS and RD signals. Maximum throughput for the AD7899 is 400 kSPS. The AD7899 is available in a 28-lead SOIC and SSOP packages. 1. The AD7899 features a fast (2.2 s) ADC allowing throughput rates of up to 400 kSPS. 2. The AD7899 operates from a single 5 V supply and consumes only 80 mW typ making it ideal for low power and portable applications. 3. The part offers a high-speed parallel interface. The interface can operate in 3 V and 5 V mode allowing for easy connection to 3 V or 5 V microprocessors, microcontrollers, and digital signal processors. 4. The part is offered in three versions with different analog input ranges. The AD7899-1 offers the standard industrial ranges of 10 V and 5 V; the AD7899-2 offers a unipolar range of 0 V to 2.5 or 0 V to 5 V, and the AD7899-3 has an input range of 2.5 V. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 AD7899-SPECIFICATIONS T Parameter SAMPLE AND HOLD -0.1 dB Full Power Bandwidth -3 dB Full Power Bandwidth Aperture Delay Aperture Jitter DYNAMIC PERFORMANCE2 AD7899-1 Signal to (Noise + Distortion) Ratio3 @ 25 C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise 3 AD7899-2 Signal to (Noise + Distortion) Ratio3 @ 25 C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise 3 AD7899-3 Signal to (Noise + Distortion) Ratio3 @ 25 C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise 3 Intermodulation Distortion 3 2nd Order Terms 3rd Order Terms DC ACCURACY Resolution Relative Accuracy (INL)3 Differential Nonlinearity (DNL)3 AD7899-1 Input Voltage Range Input Current Positive Gain Error3 Negative Gain Error3 Bipolar Zero Error AD7899-2 Input Voltage Range Input Current Positive Gain Error3 Offset Error3 AD7899-3 Input Voltage Range Input Current Positive Gain Error3 Negative Gain Error3 Bipolar Zero Error REFERENCE INPUT/OUTPUT VREF IN Input Voltage Range VREF IN Input Capacitance4 VREF OUT Output Voltage VREF OUT Error @ 25 C VREF OUT Error T MIN to TMAX VREF OUT Temperature Coefficient VREF OUT Output Impedance A Version1 500 4.5 20 25 (VDD = 5 V 5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal, all specifications 5% and 5 V 5% unless otherwise noted.) MIN to TMAX and valid for VDRIVE = 3 V B Version1 500 4.5 20 25 S Version1 500 4.5 20 25 Unit kHz typ MHz typ ns max ps typ fIN = 100 kHz, fS = 400 kSPS Test Conditions/Comments 78 78 -84 -86 78 78 -84 -86 78 77 -82 -85 dB min dB min dB max dB max 78 77 -82 -82 dB min dB min dB max dB max 78 77 -84 -86 -89 -89 14 2 1 5, 10 0.8, 0.8 10 10 12 0 to 2.5 0 to 5 0.4, 800 14 10 2.5 0.8 14 14 14 2.375/2.625 10 2.5 10 20 25 6 78 77 -84 -86 -89 -89 14 1.5 1 5, 10 0.8, 0.8 8 8 8 -89 -89 14 2 1 dB min dB min dB max dB max fa = 49 kHz, fb = 50 kHz dB typ dB typ Bits LSB max LSB max Volts mA max LSB max LSB max LSB max Volts A max LSB max LSB max VIN = 2.5 V, VIN = 5 V No Missing Codes Guaranteed 12 12 12 VIN = -5 V and -10 V Respectively 2.5 0.8 12 12 12 2.375/2.625 10 2.5 10 20 25 6 2.375/2.625 10 2.5 10 25 25 6 Volts mA max LSB max LSB max LSB max VMIN/VMAX pF max V nom mV max mV max ppm/ C typ k typ VIN = -2.5 V 2.5 V 5% See Reference Section -2- REV. A AD7899 Parameter LOGIC INPUTS A Version1 VDRIVE/2 + 0.4 VDRIVE/2 - 0.4 10 10 VDRIVE - 0.4 0.4 B Version1 VDRIVE/2 + 0.4 VDRIVE/2 - 0.4 10 10 VDRIVE - 0.4 0.4 S Version1 VDRIVE/2 + 0.4 VDRIVE/2 - 0.4 10 10 VDRIVE - 0.4 0.4 Unit V min V max A max pF max V min V max Test Conditions/Comments VDD = 5 V 5% VDD = 5 V 5% Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, C IN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB13-DB0 High Impedance Leakage Current Capacitance4 Output Coding AD7899-1, AD7899-3 AD7899-2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2, 3 Throughput Time POWER REQUIREMENTS VDD IDD Normal Mode Standby Mode Power Dissipation Normal Mode Standby Mode ISOURCE = 400 A ISINK = 1.6 mA 10 10 10 10 10 10 A max pF max Two's Complement Straight (Natural) Binary 2.2 0.3 400 5 25 20 2.2 0.3 400 5 25 20 2.2 0.3 400 5 25 20 s max s max kSPS max V nom mA max A max Typically 16 mA (5 A typ) Logic Inputs = 0 V or VDD Typically 80 mW, VDD = 5 V 125 100 125 100 125 125 mW max W max NOTES 1 Temperature Ranges are as follows : A, B Versions: -40 C to +85 C. S Version: -55C to +125C. 2 Performance measured through full channel (SHA and ADC). 3 See Terminology. 4 Sample tested @ 25C to ensure compliance. Specifications subject to change without notice. REV. A -3- AD7899 TIMING CHARACTERISTICS1, 2 (V to TMAX and valid for VDRIVE = 3 V Parameter tCONV tACQ tEOC tWAKE-UP - External VREF5 t1 t2 Read Operation t3 t4 t5 t6 3 t7 4 t8 External Clock t9 t10 t11 DD 5% and 5 V A, B and S Versions 2.2 2.46 0.3 120 180 2 35 70 = 5 V 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN 5% unless otherwise noted.) Unit s max s max s max ns min ns max s max ns min ns min Test Conditions/Comments Conversion Time, Internal Clock CLKIN = 6.5 MHz Acquisition Time EOC Pulsewidth STBY Rising Edge to CONVST Rising Edge (See Standby Mode Operation) CONVST Pulsewidth CONVST Rising Edge to BUSY Rising Edge CS to RD Setup Time CS to RD Hold Time Read Pulsewidth Data Access Time after Falling Edge of RD, VDRIVE = 5 V Data Access Time after Falling Edge of RD, VDRIVE = 3 V Bus Relinquish Time after Rising Edge of RD BUSY Falling Edge to RD Delay CLKIN to CONVST Rising Edge Setup Time CLKIN to CONVST Rising Edge Hold Time CONVST Rising Edge to CLK Falling Edge 0 0 35 35 40 5 30 0 0 20 100 ns min ns min ns min ns max ns max ns min ns max ns min ns min ns min ns min NOTES 1 Sample tested at 25C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V DRIVE) and timed from a voltage level of V DRIVE/2. 2 See Figures 5, 6, 7, and 8. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 5 Refer to the Standby Mode Operation section. Specifications subject to change without notice. 1.6mA TO OUTPUT PIN 1.6V 50pF 400 A Figure 1. Load Circuit for Access Time and Bus Relinquish Time -4- REV. A AD7899 ABSOLUTE MAXIMUM RATINGS* (TA = 25C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDRIVE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Analog Input Voltage to AGND AD7899-1 ( 10 V Range) . . . . . . . . . . . . . . . . . . . . 18 V AD7899-1 ( 5 V Range) . . . . . . . . . . . . . . . -9 V to +18 V AD7899-2 . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to +18 V AD7899-3 . . . . . . . . . . . . . . . . . . . . . . . . . . -4 V to +18 V Reference Input Voltage to AGND . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . -40C to +85C Military (S Version) . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . 220C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7899 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model AD7899AR-1 AD7899BR-1 AD7899SR-1 AD7899AR-2 AD7899AR-3 AD7899BR-3 AD7899ARS-1 AD7899ARS-2 AD7899ARS-3 Input Ranges 5 V, 10 V 5 V, 10 V 5 V, 10 V Relative Accuracy 2 LSB 1.5 LSB 2 LSB 2 LSB 2 LSB 1.5 LSB 2 LSB 2 LSB 2 LSB Temperature Range -40 -40 -55 -40 -40 -40 -40 -40 -40 C to +85 C C to +85 C C to +125 C C to +85 C C to +85 C C to +85 C C to +85 C C to +85 C C to +85 C Package Description Small Outline Small Outline Small Outline Small Outline Small Outline Small Outline Shrink Small Outline Shrink Small Outline Shrink Small Outline Package Option R-28 R-28 R-28 R-28 R-28 R-28 RS-28 RS-28 RS-28 0 V to 5 V, 0 V to 2.5 V 2.5 V 2.5 V 5 V, 10 V 0 V to 5 V, 0 V to 2.5 V 2.5 V REV. A -5- AD7899 PIN FUNCTION DESCRIPTIONS Pin No. 1 Mnemonic VREF Description Reference Input/Output. This pin is provides access to the internal reference (2.5 V 20 mV) and also allows the internal reference to be overdriven by an external reference source (2.5 V 5%). A 0.1 F decoupling capacitor should be connected between this pin and GND. Ground Pin. This pin should be connected to the system's analog ground plane. Analog Inputs. See Analog Input Section. Positive Supply Voltage, 5.0 V 5%. Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 7. Three-state outputs. Output Driver Ground. This is the ground pin of the output drivers for D13 to D0 and BUSY/EOC. It should be connected to the system's analog ground plane . This pin provides the positive supply voltage for the digital inputs and outputs. It is normally tied to VDD but may also be powered by a 3 V 10% supply which allows the inputs and outputs to be interfaced to 3 V processors and DSPs. VDRIVE should be decoupled with a 0.1 F capacitor to GND. Data Bit 6 to Data Bit 0. Three-state Outputs. BUSY/EOC Output. Digital output pin used to signify that a conversion is in progress or that a conversion has finished. The function of the BUSY/EOC is determined by the state of CONVST at the end of conversion. See the Timing and Control Section. Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs. Chip Select Input. Active low logic input. The device is selected when this input is active. Convert Start Input. Logic Input. A low to high transition on this input puts the track/hold into hold mode and starts conversion. Conversion Clock Input. CLKIN is an externally applied clock which allows the user to control the conversion rate of the AD7899. If the CLKIN input is high on the rising edge of CONVST an externally applied clock will be used as the conversion clock. If the CLKIN is low on the rising edge of CONVST the internal laser-trimmed oscillator is used as the conversion clock. Each conversion needs sixteen clock cycles in order for the conversion to be completed. The externally applied clock should have a duty cycle no greater than 60/40. The CLKIN pin can be tied to GND if an external clock is not required. Standby Mode Input. Logic input which is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. 2, 6 3, 4 5 7-13 14 15 GND VINB, VINA VDD DB13-DB7 OPGND VDRIVE 16-22 23 DB6-DB0 BUSY/EOC 24 25 26 27 RD CS CONVST CLKIN 28 STBY PIN CONFIGURATION SOIC/SSOP VREF 1 GND 2 VINB 3 VINA 4 VDD 5 GND 6 DB13 7 28 STBY 27 CLKIN 26 CONVST 25 CS 24 RD TOP VIEW 22 DB0 DB12 8 (Not to Scale) 21 DB1 DB11 9 DB10 10 DB9 11 DB8 12 DB7 13 20 DB2 19 DB3 18 DB4 17 DB5 16 DB6 15 VDRIVE AD7899 23 BUSY/EOC OPGND 14 -6- REV. A AD7899 TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 14-bit converter, this is 86.04 dB. Total Harmonic Distortion and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Positive Gain Error (AD7899-1, AD7899-3) Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7899 it is defined V2 + V3 + V4 + V5 + V6 as: THD ( dB ) = 20 log V1 2 2 2 2 2 This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 x VREF - 3/2 LSB (AD7899 at 10 V), 2 x VREF - 3/2 LSB (AD7899 at 5 V range) or VREF - 3/2 LSB (AD7899 at 2.5 V range) after the Bipolar Offset Error has been adjusted out. Positive Gain Error (AD7899-2) where V1 is the rms amplitude of the fundamental and V2, V3, V4, and V5 are the rms amplitudes of the second through the fifth harmonics. Peak Harmonic or Spurious Noise This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal 2 x VREF - 3/2 LSB (AD7899 at 10 V), 2 x VREF - 3/2 LSB (AD7899 at 0 V to 5 V range) or VREF - 3/2 LSB (AD7899 at 0 V to 2.5 V range) after the Unipolar Offset Error has been adjusted out. Unipolar Offset Error (AD7899-2) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion This is the deviation of the first code transition (00 . . . 00 to 00 . . . 01) from the ideal AGND +1/2 LSB Bipolar Zero Error (AD7899-1, AD7899-2) This is the deviation of the midscale transition (all 0s to all 1s) from the ideal AGND - 1/2 LSB. Negative Gain Error (AD7899-1, AD7899-3) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7899 is tested using two input frequencies. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal -4 x VREF + 1/2 LSB (AD7899 at 10 V), -2 x VREF + 1/2 LSB (AD7899 at 5 V range) or -VREF + 1/2 LSB (AD7899 at 2.5 V range) after Bipolar Zero Error has been adjusted out. Track/Hold Acquisition Time Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected VINA/VINB input of the AD7899. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to VINA/VINB before starting another conversion, to ensure that the part operates to specification. REV. A -7- AD7899 CONVERTER DETAILS The AD7899 is a high-speed, low-power, 14-bit A/D converter that operates from a single 5 V supply. The part contains a 2.2 s successive-approximation ADC, track/hold amplifier, an internal 2.5 V reference and a high-speed parallel interface. The part accepts an analog input range of 10 V or 5 V (AD7899-1), 0 V to 2.5 V or 0 V to 5 V (AD7899-2) and 2.5 V (AD7899-3). Overvoltage protection on the analog inputs for the part allows the input voltage to go to 18 V (AD7899-1 with 10 V input range), -9 V to +18 V (AD7899-1 with 5 V input range), -1 V to +18 V (AD7899-2) and -4 V to +18 V (AD7899-3) without causing damage. A conversion is initiated on the AD7899 by pulsing the CONVST input. On the rising edge of CONVST, the on-chip track/hold is placed into hold and the conversion is started. The BUSY/EOC output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conversion sequence. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock. An external noncontinuous clock is applied to the CLKIN pin. If, on the rising edge of CONVST, this input is high, the external clock will be used. The external clock should not start until 100 ns after the rising edge of CONVST. The optimum throughput is obtained by using the internally generated clock--see Using an External Clock. The BUSY/EOC signal indicates the end of the conversion, and at this time the Track and Hold returns to tracking mode. The conversion results can be read at the end of the conversion (indicated by BUSY/EOC going low) via a 14-bit parallel data bus with standard CS and RD signals--see Timing and Control. Conversion time for the AD7899 is 2.2 s and the track/hold acquisition time is 0.3 s. To obtain optimum performance from the part, the read operation should not occur during a conversion or during the 150 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 400 kHz and achieve data sheet specifications. CIRCUIT DESCRIPTION Track/Hold Section external CONVST signal and the track/hold actually going into hold) is typically 15 ns and, more importantly, is well matched from device to device. It allows multiple AD7899s to sample more than one channel simultaneously. At the end of a conversion, the part returns to its tracking mode. The acquisition time of the track/hold amplifier begins at this point. Reference Section The AD7899 contains a single reference pin, labelled VREF, which either provides access to the part's own 2.5 V reference or allows an external 2.5 V reference to be connected to provide the reference source for the part. The part is specified with a 2.5 V reference voltage. To use the internal reference as the reference source for the AD7899, simply connect a 0.1 F capacitor from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is required for use external to the AD7899, it should be buffered, as the part has a FET switch in series with the reference output resulting in a source impedance for this output of 6 k nominal. The tolerance on the internal reference is 10 mV at 25C with a typical temperature coefficient of 25 ppm/C and a maximum error over temperature of 20 mV. If the application requires a reference with a tighter tolerance or the AD7899 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference will effectively overdrive the internal reference and thus provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of 100 A. Suitable reference sources for the AD7899 include the AD680, AD780, REF192, and REF43 precision 2.5 V references. Analog Input Section The track/hold amplifier on the AD7899 allows the ADCs to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 400 kSPS (i.e., the track/hold can handle input frequencies in excess of 200 kHz). The track/hold amplifier's acquire input signals to 14-bit accuracy in less than 300 ns The operation of the track/hold is essentially transparent to the user. The track/hold amplifier samples the input channel on the rising edge of CONVST. The aperture time for the track/hold (i.e., the delay time between the The AD7899 is offered as three part types, the AD7899-1 where the input can be configured for 10 V or a 5 V input voltage range, the AD7899-2 where the input can be configured for 0 V to 5 V or a 0 V to 2.5 V input voltage range and the AD7899-3 which handles input voltage range 2.5 V. The amount of current flowing into the analog input will depend on the analog input range and the analog input voltage. The maximum current flows when negative full-scale is applied. AD7899-1 Figure 2 shows the analog input section of the AD7899-1. The input can be configured for 5 V or 10 V operation on the AD7899-1. For 5 V operation, the VINA and VINB inputs are tied together and the input voltage is applied to both. For 10 V operation, the VINB input is tied to AGND and the input voltage is applied to the VINA input. The VINA and VINB inputs are symmetrical and fully interchangeable. -8- REV. A AD7899 AD7899-2 AD7899-1 2.5V REFERENCE 6k TO ADC REFERENCE CIRCUITRY R1 VINA R2 TO INTERNAL COMPARATOR TRACK/HOLD VREF Figure 3 shows the analog input section of the AD7899-2. Each input can be configured for 0 V to 5 V operation or 0 V to 2.5 V operation. For 0 V to 5 V operation, the VINB input is tied to GND and the input voltage is applied to the VINA input. For 0 V to 2.5 V operation, the VINA and VINB inputs are tied together and the input voltage is applied to both. The VINA and VINB inputs are symmetrical and fully interchangeable. For the AD7899-2, R1 = 4 k and R2 = 4 k. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FSR/ 16384 = 2.5 V/16384 = 0.153 mV, and 5 V/16384 = 0.305 mV, for the 0 to 2.5 V and the 0 to 5 V options respectively. Table II shows the ideal input and output transfer function for the AD7899-2. AD7899-2 2.5V REFERENCE 6k TO ADC REFERENCE CIRCUITRY VINB R3 R4 GND Figure 2. AD7899-1 Analog Input Structure For the AD7899-1, R1 = 4 k, R2 = 16 k, R3 = 16 k and R4 = 8 k. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/16384. For the 5 V range, 1 LSB = 10 V/16384 = 610.4 V. For the 10 V range, 1 LSB = 20 V/16384 = 1.22 mV. Output coding is two's complement binary with 1 LSB = FSR/16384. The ideal input/output transfer function for the AD7899-1 is shown in Table I. Table I. Ideal Input/Output Code Table for the AD7899-1 VREF VINA R1 TO INTERNAL COMPARATOR TRACK/HOLD VINB R2 Analog Input1 +FSR/2 - 3/2 LSB2 +FSR/2 - 5/2 LSB +FSR/2 - 7/2 LSB GND + 3/2 LSB GND + 1/2 LSB GND - 1/2 LSB GND - 3/2 LSB -FSR/2 + 5/2 LSB -FSR/2 + 3/2 LSB -FSR/2 + 1/2 LSB Digital Output Code Transition 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 Figure 3. AD7899-2 Analog Input Structure Table II. Ideal Input/Output Code Table for the AD7899-2 Analog Input1 +FSR - 3/2 LSB2 +FSR - 5/2 LSB +FSR - 7/2 LSB GND + 5/2 LSB GND + 3/2 LSB GND + 1/2 LSB Digital Output Code Transition 111 . . . 110 to 111 . . . 111 111 . . . 101 to 111 . . . 110 111 . . . 100 to 111 . . . 101 000 . . . 010 to 000 . . . 011 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 NOTES 1 FSR is full-scale range and is 20 V for the 10 V range and 10 V for the 5 V range, with VREF = 2.5 V. 2 1 LSB = FSR/16384 = 1.22 mV (10 V - AD7899-1) and 610.4 V (5 V - AD7899-1) with VREF = 2.5 V. NOTES 1 FSR is Full-Scale Range and is 0 to 2.5 V and 0 to 5 V for AD7899-2 with V REF = 2.5 V. 2 1 LSB = FSR/16384 and is 0.153 mV (0 to 2.5 V) and 0.305 mV (0 to 5 V) for AD7899-2 with VREF = 2.5 V. REV. A -9- AD7899 AD7899-3 Figure 4 shows the analog input section of the AD7899-3. The analog input range is 2.5 V on the VINA input. The VINB input can be left unconnected but if it is connected to a potential then that potential must be GND. AD7899-3 2.5V REFERENCE 6k TO ADC REFERENCE CIRCUITRY R1 VINA R2 TO INTERNAL COMPARATOR TRACK/HOLD TIMING AND CONTROL Starting a Conversion The conversion is initiated by applying a rising edge to the CONVST signal. This places the track/hold into hold mode and starts the conversion. The status of the conversion is indicated by the dual function signal BUSY/EOC. The AD7899 can operate in two conversion modes, EOC (End Of Conversion) mode and BUSY mode. The operating mode is determined by the state of CONVST at the end of the conversion. Selecting a Conversion Clock VREF VINB The AD7899 has an internal laser trimmed oscillator which can be used to control the conversion process. Alternatively an external clock source can be used to control the conversion process. The highest external clock frequency allowed is 6.5 MHz. This means a conversion time of 2.46 s compared to 2.2 s using the internal clock. However in some instances it may be useful to use an external clock when high throughput rates are not required. For example two or more AD7899s may be synchronized by using the same external clock for all devices. In this way there is no latency between output logic signals due to differences in the frequency of the internal clock oscillators. On the rising edge of CONVST the AD7899 will examine the status of the CLKIN pin. If this pin is low it will use the internal laser trimmed oscillator as the conversion clock. If the CLKIN pin is high the AD7899 will wait for an external clock to be supplied to this pin which will then be used as the conversion clock. The first falling edge of the external clock should not happen for at least 100 ns after the rising edge of CONVST to ensure correct operation. Figure 5 shows how the BUSY/EOC output is synchronized to the CLKIN signal. Each conversion requires 16 clocks. The result of the conversion is transferred to the output data register on the falling edge of the 15th clock cycle. When the internal clock is selected the status of the CLKIN pin is free to change during conversion but the CLKIN setup and hold times must be observed in order to ensure that the correct conversion clock is used. The CLKIN pin can also be tied low permanently if the internal conversion clock is to be used. t9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLKIN Figure 4. AD7899-3 Analog Input Structure For the AD7899-3, R1 = 4 k and R2 = 4 k. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/16384. Output coding is two's complement binary with 1 LSB = FSR/ 16384 = 5 V/16384 = 610.4 V. The ideal input/output transfer function for the AD7899-3 is shown in Table III. Table III. Ideal Input/Output Code Table for the AD7899-3 Analog Inputl +FSR/2 - 3/2 LSB2 +FSR/2 - 5/2 LSB +FSR/2 - 7/2 LSB GND + 3/2 LSB GND + 1/2 LSB GND - 1/2 LSB GND - 3/2 LSB -FSR/2 + 5/2 LSB -FSR/2 + 3/2 LSB -FSR/2 + 1/2 LSB Digital Output Code Transition 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 t 11 CONVST BUSY/EOC RD CS NOTES 1 FSR is full-scale range is 5 V, with V REF = 2.5 V 2 1 LSB = FSR/16384 = 610.4 V ( 2.5 V - AD7899-3) with V REF = 2.5 V. Figure 5. Using an External Clock -10- REV. A AD7899 t 10 t9 CLKIN t1 CONVST t ACQ t EOC t2 t8 t CONV t5 t3 t4 QUIET TIME BUSY/EOC RD CS THREE-STATE DATA THREE-STATE t6 t7 Figure 6. Conversion Sequence Timing Diagram (EOC Mode) t 10 t9 CLKIN t1 CONVST t ACQ t8 BUSY/EOC QUIET TIME t CONV RD t5 t3 t4 CS THREE-STATE DATA THREE-STATE t6 t7 Figure 7. Conversion Sequence Timing Diagram (BUSY Mode) EOC Mode Continuous Conversion Mode The CONVST signal is normally high. Pulsing the CONVST low will initiate a conversion on its rising edge. The state of the CONVST signal is checked at the end of conversion. Since the CONVST will be high when this happens the AD7899 BUSY/ EOC pin will take on its EOC function and bring the BUSY/EOC line low for one clock period before returning high again. In this mode the EOC can be tied to the RD and CS signals to allow automatic reading of the conversion result if required. The timing diagram for operation in EOC mode is shown in Figure 6. BUSY Mode When the AD7899 is used with an external clock, connecting the CLKIN and CONVST signals together will cause the AD7899 to continuously perform conversions. As each conversion completes the BUSY/EOC pin will pulse low for one clock period (EOC function) indicating that the conversion result is available. Figure 8 shows the timing and control sequence of the AD7899 in Continuous Conversion Mode. Reading Data from the AD7899 The CONVST signal is normally low. Pulsing the CONVST high will initiate a conversion on its rising edge. The state of the CONVST signal is checked at the end of conversion. Since the CONVST will be low when this happens the AD7899 BUSY/ EOC pin will take on its BUSY function will bring BUSY/EOC low, indicating that the conversion is complete. BUSY/EOC will remain low until the next rising edge of CONVST where BUSY/ EOC returns high. The timing diagram for operation in BUSY mode is shown in Figure 7. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals. The CS and RD inputs are internally gated to enable the conversion result onto the data bus. The data lines DB0 to DB13 leave their high impedance state when both CS and RD are logic low. Therefore CS may be permanently tied logic low and the RD signal used to access the conversion result if required. Figures 6 and 7 show a timing specification called "Quiet Time." This is the amount of time which should be left after a read operation and before the next conversion is initiated. The quiet time depends heavily on data bus capacitance but a figure of 50 ns to 100 ns is typical, with a worst case figure of 150 ns. REV. A -11- AD7899 1 CONVST/ CLKIN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EOC START OF NEW CONVERSION (INPUT SAMPLED) CONVERSION COMPLETE Figure 8. Continuous Conversion Mode Standby Mode Operation Signal-to-Noise Ratio (SNR) The AD7899 has a Standby Mode whereby the device can be placed in a low current consumption mode (5 A typ). The AD7899 is placed in Standby by bringing the logic input STBY low. The AD7899 can be powered again up for normal operation by bringing STBY logic high. The output data buffers are still operational while the AD7899 is in Standby. This means the user can still continue to access the conversion results while the AD7899 is in standby. This feature can be used to reduce the average power consumption in a system using low throughput rates. To reduce the average power consumption, the AD7899 can be placed in standby at the end of each conversion sequence and taken out of standby again prior to the start of the next conversion sequence. The time it takes the AD7899 to come out of standby is called the "wake up" time. This wake-up time will limit the maximum throughput rate at which the AD7899 can be operated when powering down between conversions. When the AD7899 is used with the internal reference, the reference capacitor will begin to discharge during standby. The voltage remaining on the capacitor at wake-up time will depend upon the standby time and hence affect the wake-up time. The minimum wake-up time is typically 2 s. The maximum wake-up time will be when the AD7899 has been in standby long enough for the reference capacitor to fully discharge. The wake-up time in this case will typically be 15 ms. The AD7899 will wake up in approximately 1 s when using an external reference, regardless of sleep time. When operating the AD7899 in a Standby mode between conversions, the power savings can be significant. For example, with a throughput rate of 10 kSPS and an external reference, the AD7899 will be powered up for 4.2 s out of every 100 s (2 s for wake-up time and 2.2 s for conversion time). Therefore, the average power consumption drops to 80 mW x 4.2% or approximately 3.36 mW. AD7899 DYNAMIC SPECIFICATIONS SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for an ideal 14-bit converter, SNR = 86.04 dB. Figure 9 shows a histogram plot for 8192 conversions of a dc input using the AD7899 with 5 V supply. The analog input was set at the center of a code transition. It can be seen that most of the codes appear in one output bin, indicating very good noise performance from the ADC. 7000 (1) 6000 5000 4000 3000 2000 1000 0 Figure 9. Histogram of 8192 Conversions of a DC Input The AD7899 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as Integral and Differential Nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information on the ADC's effect on the spectral content of the input signal. Hence, the parameters for which the AD7899 is specified include SNR, harmonic distortion, intermodulation distortion, and peak harmonics. These terms are discussed in more detail in the following sections. The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the analog input. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 10 shows a typical 4096 point FFT plot of the AD7899 with an input signal of 100 kHz and a sampling frequency of 400 kHz. The SNR obtained from this graph is 80.5 dB. It should be noted that the harmonics are taken into account when calculating the SNR. -12- REV. A AD7899 0 -20 -40 fs = 400kHz fIN = 100kHz SNR = 80.5dB -60 dB second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input consists of two, equal amplitude, low distortion sine waves. Figure 12 shows a typical IMD plot for the AD7899. 0 -20 -40 -80 -100 -120 -140 dB 0 50000 100000 FREQUENCY - Hz 150000 200000 -60 -80 Figure 10. FFT Plot Effective Number of Bits -100 -120 The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to obtain a measure of performance expressed in effective number of bits (N). N= SNR - 1.76 6.02 -140 0 50000 100000 FREQUENCY - Hz 150000 200000 (2) AC Linearity Plots Figure 12. IMD Plot The effective number of bits for a device can be calculated directly from its measured SNR. Figure 11 shows a typical plot of effective number of bits versus frequency for an AD7899. 14 13 12 11 10 +125 C 9 +25 C -55 C The plots in Figure 13 show typical DNL and INL for the AD7899. 1.00 0.50 ENOB 8 7 6 5 4 3 2 1 0 0 100 1000 INPUT FREQUENCY - kHz DNL - LSB 0 -0.50 -1.00 10000 1.00 0 2000 4000 6000 8000 10000 12000 ADC - Code 14000 16000 Figure 11. Effective Numbers of Bits vs. Frequency Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb) while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7899 is tested using two input frequencies. In this case the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the 0.50 INL - LSB 0 -0.50 -1.00 0 2000 4000 6000 8000 10000 12000 ADC - Code 14000 16000 Figure 13. Typical DNL and INL Plots REV. A -13- AD7899 MICROPROCESSOR INTERFACING AD7899-TMS320C5x Interface The high-speed parallel interface of the AD7899 allows easy interfacing to most DSPs and microprocessors. The AD7899 interface of the AD7899 consists of the data lines (DB0 to DB13), CS, RD, and BUSY/EOC. AD7899-ADSP-21xx Interface Figure 14 shows an interface between the AD7899 and the ADSP-21xx. The CONVST signal can be generated by the ADSP-21xx or from some other external source. Figure 14 shows the CS being generated by a combination of the DMS signal and the address bus of the ADSP-21xx. In this way the AD7899 is mapped into the data memory space of the ADSP-21xx. The AD7899 BUSY/EOC line provides an interrupt to the ADSP-21xx when the conversion is complete. The conversion result can then be read from the AD7899 using a read operation. The AD7899 is read using the following instruction MR0 = DM(ADC) Figure 15 shows an interface between the AD7899 and the TMS320C5x. As with the previous interfaces, conversion can be initiated from the TMS320C5x or from an external source and the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7899 derived from the DS signal and a decode of the address bus. This maps the AD7899 into external data memory. The RD signal from the TMS320 is used to enable the ADC data onto the data bus. The AD7899 has a fast parallel bus so there are no wait state requirements. The following instruction is used to read the conversion results from the AD7899: IN D,ADC where D is Data Memory address and ADC is the AD7899 address. TMS320C5x ADDRESS DECODE CS VIN RD RD A0-A13 DS where MR0 is the ADSP-21xx MR0 register and ADC is the AD7899 address. ADSP-21xx ADDRESS DECODE CS VIN RD RD A0-A13 DMS DB0-DB13 D0-D13 AD7899 BUSY/EOC INTn PA0 DB0-DB13 D8-D21 CONVST AD7899 BUSY/EOC CONVST IRQn DT1/F0 Figure 15. AD7899-TMS320C5x Interface Figure 14. AD7899-ADSP-21xx Interface -14- REV. A AD7899 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Small Outline (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 1 14 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 45 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead Shrink Small Outline (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 0.311 (7.9) 0.301 (7.64) 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.79) 0.066 (1.67) 0.212 (5.38) 0.205 (5.21) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 8 0.015 (0.38) 0 SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) AD7899-Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Edit to Timing page heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to Converter Details section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edit to Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REV. A -15- -16- C01365-0-6/01(A) PRINTED IN U.S.A. |
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